As the processing power of today's computers exponentially increase, attention is turned to other components of the computer system to achieve corresponding system performance gains. One such component is memory. Memory manufacturers must, accordingly, devote efforts to enhancing performance while minimizing costs. This objective becomes problematic as the demands for device miniaturization drives design rules to 0.18 microns and below. It recognized that high quality dielectrics are needed in such devices to achieve device performance both in terms of speed and longevity.
Conventional non-volatile memory semiconductor devices comprise a stacked gate structure as illustrated in FIG. 1A. Typically, a floating gate 105 comprising polycrystalline silicon (polysilicon) is deposited onto a semiconductor substrate or epitaxial layer grown thereon (not shown) with a thin tunnel oxide layer 107, therebetween. A dielectric layer 103 (e.g., oxide/nitride/oxide, nitride/oxide, thermal oxide, HTO, etc.), is formed on floating gate 105 and a control gate 101, such as polysilicon, is formed on dielectric layer 103. Through manipulation of the control gate, electrons "tunnel" through the tunnel oxide to or from the floating gate. This tunnel effect is known as Fowler-Nordheim tunneling. The read/write capability of the memory cell relates to the charge state of the floating gate electrode, which is a function of the threshold voltage of the MOS transistor. The current through the tunnel oxide turns the memory cell on or off and, therefore, is instrumental in the performance of the cell.
To ensure that the appropriate amount of current flows through the tunnel oxide, conventional memory cells require that the tunnel oxide film be very thin, e.g., about 100 .ANG. for fast operations. Unfortunately, thin tunnel oxide layers are accompanied by parasitic capacitance problems. Also, the breakdown voltage may fall below unacceptable levels. A poor breakdown voltage level may be attributed to trapping of electric charge in the oxide. This trapping effect can be mitigated through the use of higher quality oxides, which trap less charge and, thus, can withstand higher induced voltages before breakdown. In addition, the tunnel oxide layer may undergo degradation during photolithographic processing.
Basically, the engineering tradeoff is between speed of read/write operations and tunnel oxide thickness. A thinner tunnel oxide layer creates a stronger electric field between the gate and the source or drain. As a result of this intense electric field, the electrons in the thin tunnel oxide layer travel faster than they would in a thicker tunnel oxide layer. This rush of electrons translates into improved speed of the memory cell operations. However, as the tunnel oxide layer is thinned, pin holes emerge, resulting in reliability problems. Consequently, a minimal thickness must be maintained to avoid potential reliability issues. A standard test for determining oxide reliability is high temperature retention bake (HTRB).
It is recognized that high quality tunnel oxides serve a crucial role in the fabrication of semiconductor devices. A variety of methods have been developed in an attempt to optimize the engineering tradeoff.
U.S. Pat. No. 5,371,027 discloses that implantation of the tunnel oxide with a heavy ion, such as arsenic, can improve the tunnel oxide quality. During ion implantation, silicon atoms are dislodged from the underlying silicon into the tunnel oxide, producing a silicon enriched region within the tunnel oxide. The altered tunnel oxide layer subsequently assumes new tunneling characteristics. Of significance is the fact that thicker tunnel oxides can be used without compromising the level of current flow through the tunnel. That is, the current flow is comparable to that exhibited by thinner tunnel oxides. This method also avoids oxide degradation due to photolithographic processing by eliminating the need for direct contact between the tunnel oxide and photoresist layers. This method improves tunnel oxide behavior by allowing the use of a thicker oxide (about 200 .ANG.) to achieve current flow comparable to that of a thin oxide (about 100 .ANG. or less).
Another approach is disclosed in U.S. Pat. No. 5,591,681 and comprises oxidizing the substrate region containing a heavily-doped N+ layer. Next, an annealing process, under a gettering ambient, densities the oxide and provides doping at the oxide surface. A further oxidation step thickens the oxide. Subsequently, an NO anneal introduces nitrogen to improve the characteristics of the tunnel oxide as well as the gate. Because both floating gate and tunnel oxide are doped, doping control is more complex than the monitoring of a single layer.
In another process, as described in U.S. Pat. No. 4,789,883, the floating gate is formed of amorphous silicon instead of the conventional polysilicon. The amorphous silicon, about 2500 .ANG. in thickness, is ion implanted with an arsenic or phosphorous dopant. Whereas the patent is concerned with in situ doping of the amorphous silicon.
There remains a need for non-volatile memory semiconductor devices having improved tunnel oxide quality, particularly for semiconductor devices having a design rule of about 0.18 microns and under.